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the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all devices/types available in every country. please check with local nec representative for availability and additional information. ? 2002 mos integrated circuit pd16772b 480-output tft-lcd source driver (compatible with 64-gray scales) data sheet document no. s15996ej1v0ds00 (1st edition) date published july 2002 ns cp (k) printed in japan the mark ! ! ! ! shows major revised points. description the pd16772b is a source driver for tft-lcds capable of dealing with displays with 64-gray scales. data input is based on digital input configured as 6 bits by 6 dots (2 pixels), which can realize a full-color display of 260,000 colors by output of 64 values -corrected by an internal d/a converter and 5-by-2 external power modules. because the output dynamic range is as large as v ss2 + 0.1 v to v dd2 ? 0.1 v, level inversion operation of the lcd?s common electrode is rendered unnecessary. also, to be able to deal with dot-line inversion, n-line inversion and column line inversion when mounted on a single side, this source driver is equipped with a built-in 6-bit d/a converter circuit whose odd output pins and even output pins respectively output gray scale voltages of differing polarity. assuring a clock frequency of 45 mhz when driving at 2.3 v, this driver is applicable to uxga-standard tft-lcd panels. features ? cmos level input (2.3 to 3.6 v) ? 480 outputs ? input of 6 bits (gradation data) by 6 dots ? capable of outputting 64 values by means of 5-by-2 external power modules (10 units) and a d/a converter (r-dac) ? logic power supply voltage (v dd1 ): 2.3 to 3.6 v ? driver power supply voltage (v dd2 ): 8.5 v 0.5 v ? output dynamic range: v ss2 + 0.1 v to v dd2 ? 0.1 v ? high-speed data transfer: f clk = 45 mhz (internal data transfer speed when operating at v dd1 = 2.3 v) ? apply for dot-line inversion, n-line inversion and column line inversion ? output voltage polarity inversion function (pol) ? display data inversion function (pol21, pol22) ? current consumption reduction function (lpc, bcont) ordering information part number package pd16772bn-xxx tcp (tab package) remark the tcp?s external shape is customized. to order the required shape, so please contact one of our sales representatives.
data sheet s15996ej1v0ds 2 pd16772b 1. block diagram sthl v dd1 v ss1 v dd2 v ss2 s 2 s 1 v 0 to v 9 pol d 00 to d 05 c 1 c 2 c 79 c 80 stb clk 80-bit bidirectional shift register data register latch level shifter d/a converter voltage follower output r,/l sthr d 10 to d 15 d 20 to d 25 s 3 s 480 pol21, pol22 d 30 to d 35 d 40 to d 45 d 50 to d 55 lpc bcont remark /xxx indicates active low si gnal. 2. relationship between output circuit and d/a converter s 1 s 2 s 479 6-bit d/a converter s 480 v 4 5 5 pol multi- plexer v 9 v 0 v 5
data sheet s15996ej1v0ds 3 pd16772b 3. pin configuration ( pd16772b) (copper foil surface, face-up) s 480 s 479 sthl s 478 d 55 s 477 d 54 d 53 d 52 d 51 d 50 d 45 d 44 d 43 d 42 d 41 d 40 d 35 d 34 d 33 d 32 d 31 d 30 v dd1 r , /l v 9 v 8 v 7 v 6 v 5 v dd2 v ss2 bcont v 4 v 3 v 2 v 1 v 0 v ss1 lpc clk stb pol pol21 pol22 d 25 d 24 d 23 d 22 d 21 d 20 d 15 d 14 d 13 d 12 d 11 d 10 d 05 d 04 d 03 s 4 d 02 s 3 d 01 s 2 d 00 s 1 sthr co pp er foil surface remark this figure does not specify the tcp package.
data sheet s15996ej1v0ds 4 pd16772b 4. pin functions (1/2) pin symbol pin name i/o description s 1 to s 480 driver output the d/a converted 64-gray-scale analog voltage is output. d 00 to d 05 d 10 to d 15 d 20 to d 25 d 30 to d 35 d 40 to d 45 d 50 to d 55 display data input the display data is input with a width of 36 bits, viz., the gray scale data (6 bits) by 6 dots (2 pixels). d x0 : lsb, d x5 : msb r,/l shift direction control input these refer to the start pulse i/o pins when driver ics are connected in cascade. the shift directions of the shift registers are as follows. r,/l = h: sthr input, s 1 s 480 , sthl output r,/l = l: sthl input, s 480 s 1 , sthr output sthr right shift start pulse i/o sthl left shift start pulse i/o these refer to the start pulse i/o pins when driver ics are connected in cascade. fetching of display data starts when h is read at the rising edge of clk. r,/l = h (right shift): sthr input, sthl output r,/l = l (left shift): sthl input, sthr output a high level should be input as the pulse of one cycle of the clock signal. if the start pulse input is more than 2 clk, the fist 1 clk of the high-level input is valid. clk shift clock input refers to the shift register?s shift clock input. the display data is incorporated into the data register at the rising edge. at the rising edge of the 80 th clock after the start pulse input, the start pulse output reaches the high level, thus becoming the start pulse of the next-level driver. if 82 clock pulses are input after input of the start pulse, input of display data is halted automatically. the contents of the shift register are cleared at the stb?s rising edge. stb latch input the contents of the data register are transferred to the latch circuit at the rising edge. and, at the falling edge, the gray scale voltage is supplied to the driver. it is necessary to ensure input of one pulse per horizontal period. pol polarity input pol = l: the s 2n?1 output uses v 0 to v 4 as the reference supply. the s 2n output uses v 5 to v 9 as the reference supply. pol = h: the s 2n?1 output uses v 5 to v 9 as the reference supply. the s 2n output uses v 0 to v 4 as the reference supply. s 2n?1 indicates the odd output: and s 2n indicates the even output. input of the pol signal is allowed the setup time(t pol - stb ) with respect to stb?s rising edge. pol21, pol22 data inversion input data inversion can invert when display data is loaded. pol21, pol22 = h: data inversion loads display data after inverting it. pol21, pol22 = l: data inversion does not invert input data. pol21: d 00 to d 05 , d 10 to d 15 , d 20 to d 25 pol22: d 30 to d 35 , d 40 to d 45 , d 50 to d 55 lpc low power control input the current consumption of v dd2 is lowered by controlling the constant current source of the output amplifier. this pin is pulled up to the v dd1 power supply inside the ic. for details, see 9. current consumption reduction function. bcont bias control input this pin can be used to finely control the bias current inside the output amplifier. when this fine-control function is not required, leave this pin open. for details, see 9. current consumption reduction function.
data sheet s15996ej1v0ds 5 pd16772b (2/2) pin symbol pin name i/o description v 0 to v 9 -corrected power supplies ? input the -corrected power supplies from outside by using operational amplifier. make sure to maintain the following relationships. during the gray scale voltage output, be sure to keep the gray scale level power supply at a constant level. v dd2 ? 0.1 v v 0 > v 1 > v 2 > v 3 > v 4 0.5 v dd2 0.5 v dd2 v 5 > v 6 > v 7 > v 8 > v 9 v ss2 + 0.1 v v dd1 logic power supply ? 2.3 to 3.6 v v dd2 driver power supply ? 8.5 v 0.5 v v ss1 logic ground ? grounding v ss2 driver ground ? grounding cautions 1. the power start sequence must be v dd1 , logic input, and v dd2 & v 0 to v 9 in that order. reverse this sequence to shut down (simultaneous power application to v dd2 and v 0 to v 9 is possible.). 2. to stabilize the supply voltage, please be sure to insert a 0.1 f bypass capacitor between v dd1 -v ss1 and v dd2 -v ss2 . furthermore, for increased precision of the d/a converter, insertion of a bypass capacitor of about 0.01 f is also advised between the -corrected power supply terminals (v 0 , v 1 , v 2 ,....., v 9 ) and v ss2 .
data sheet s15996ej1v0ds 6 pd16772b 5. relationship between input data and output voltage value the pd16772b incorporates a 6-bit d/a converter whose odd output pins and even output pins output respectively gray scale voltages of differing polarity with respect to the lcd?s counter electrode (common electrode) voltage. the d/a converter consists of ladder resistors and switches. the ladder resistors (r0 to r62) are designed so that the ratio of lcd panel -compensated voltages to v 0 ? to v 63 ? and v 0 ? to v 63 ? is almost equivalent. for the 2 sets of five -compensated power supplies, v 0 to v 4 and v 5 to v 9 , respectively, input gray scale voltages of the same polarity with respect to the common voltage. when fine gray scale voltage precision is not necessary, there is no need to connect a voltage follower circuit to the -compensated power supplies v 1 to v 3 and v 6 to v 8 . figure 5?1 shows the relationship between the driving voltages such as liquid-crystal driving voltages v dd2 and v ss2 , common electrode potential v com , and -corrected voltages v 0 to v 9 and the input data. be sure to maintain the voltage relationships as follows. v dd2 ? 0.1 v v 0 > v 1 > v 2 > v 3 > v 4 0.5 v dd2 0.5 v dd2 v 5 > v 6 > v 7 > v 8 > v 9 v ss2 + 0.1 v figure 5?2 shows -corrected power supply voltage and ladder resistors ratio and figure 5?3 shows the relationship between the input data and the output voltage and the resistance values of the resistor strings. figure 5?1. relationship between input data and -corrected power supplies v 1 v 2 v 3 v 4 v ss2 00 10 20 30 3f v 0 v 6 v 8 v dd2 16 v 9 16 16 16 15 split interval 0.1 v 0.1 v input data (hex) 15 16 16 0.5 v dd2 v 5 v 7
data sheet s15996ej1v0ds 7 pd16772b figure 5?2. -corrected power supply voltage and ladder resistors ratio v 0 v 17 ?? v 16 ?? v 15 ?? v 1 ?? v 2 ?? v 0 ?? v 61 ?? v 60 ?? v 49 ?? v 48 ?? v 47 ?? r60 r59 r49 r48 r47 r46 v 6 r61 r17 r16 r15 r14 v 8 v 62 ?? r62 v 9 v 63 ?? v 5 v 47 ? v 48 ? v 49 ? v 61 ? v 62 ? v 63 ? v 2 ? v 3 ? v 15 ? v 16 ? v 17 ? r2 r3 r14 r15 r16 r17 v 1 r1 r46 r47 r48 r49 r60 r61 r62 v 3 v 4 v 1 ? r0 r2 r1 r0 v 0 ? remark the resistance ratio1 is a relative ratio in the case of setting the minimum resistance value to 1. the resistance ratio2 is a relative ratio in the case of setting the total resistance to 1. caution there is no connection between v 4 and v 5 terminal in the chip. rn value ratio (1) ratio (2) r0 722 7.68 0.0454 r1 628 6.68 0.0395 r2 628 6.68 0.0395 r3 596 6.34 0.0375 r4 596 6.34 0.0375 r5 502 5.34 0.0315 r6 470 5.00 0.0295 r7 454 4.83 0.0285 r8 454 4.83 0.0285 r9 408 4.34 0.0256 r10 330 3.51 0.0207 r11 298 3.17 0.0187 r12 266 2.83 0.0167 r13 266 2.83 0.0167 r14 236 2.51 0.0148 r15 220 2.34 0.0138 r16 204 2.17 0.0128 r17 204 2.17 0.0128 r18 172 1.83 0.0108 r19 156 1.66 0.0098 r20 156 1.66 0.0098 r21 142 1.51 0.0089 r22 142 1.51 0.0089 r23 142 1.51 0.0089 r24 142 1.51 0.0089 r25 126 1.34 0.0079 r26 126 1.34 0.0079 r27 110 1.17 0.0069 r28 110 1.17 0.0069 r29 110 1.17 0.0069 r30 110 1.17 0.0069 r31 110 1.17 0.0069 r32 110 1.17 0.0069 r33 110 1.17 0.0069 r34 94 1.00 0.0059 r35 94 1.00 0.0059 r36 94 1.00 0.0059 r37 110 1.17 0.0069 r38 110 1.17 0.0069 r39 94 1.00 0.0059 r40 110 1.17 0.0069 r41 94 1.00 0.0059 r42 110 1.17 0.0069 r43 94 1.00 0.0059 r44 110 1.17 0.0069 r45 126 1.34 0.0079 r46 110 1.17 0.0069 r47 110 1.17 0.0069 r48 110 1.17 0.0069 r49 126 1.34 0.0079 r50 126 1.34 0.0079 r51 126 1.34 0.0079 r52 142 1.51 0.0089 r53 142 1.51 0.0089 r54 126 1.34 0.0079 r55 188 2.00 0.0118 r56 188 2.00 0.0118 r57 220 2.34 0.0138 r58 220 2.34 0.0138 r59 236 2.51 0.0148 r60 360 3.83 0.0226 r61 564 6.00 0.0354 r62 2022 21.51 0.1271 rtotal 15912 169.28 1.0000
data sheet s15996ej1v0ds 8 pd16772b figure 5 ? ? ? ? 3. relationship between input data and output voltage (pol21, pol22 = l) (output voltage 1) v dd2 ? 0.1 v v 0 > v 1 > v 2 > v 3 > v 4 0.5 v dd2 (output voltage 2) 0.5 v dd2 v 5 > v 6 > v 7 > v 8 > v 9 v ss2 + 0.1 v input data 00h v 0' v 0 v 0'' v 9 01h v 1' v 1 +(v 0 -v 1 ) 6352 / 7074 v 1'' v 9 +(v 8 -v 9 ) 722 / 7074 02h v 2' v 1 +(v 0 -v 1 ) 5724 / 7074 v 2'' v 9 +(v 8 -v 9 ) 1350 / 7074 03h v 3' v 1 +(v 0 -v 1 ) 5096 / 7074 v 3'' v 9 +(v 8 -v 9 ) 1978 / 7074 04h v 4' v 1 +(v 0 -v 1 ) 4500 / 7074 v 4'' v 9 +(v 8 -v 9 ) 2574 / 7074 05h v 5' v 1 +(v 0 -v 1 ) 3904 / 7074 v 5'' v 9 +(v 8 -v 9 ) 3170 / 7074 06h v 6' v 1 +(v 0 -v 1 ) 3402 / 7074 v 6'' v 9 +(v 8 -v 9 ) 3672 / 7074 07h v 7' v 1 +(v 0 -v 1 ) 2932 / 7074 v 7'' v 9 +(v 8 -v 9 ) 4142 / 7074 08h v 8' v 1 +(v 0 -v 1 ) 2478 / 7074 v 8'' v 9 +(v 8 -v 9 ) 4596 / 7074 09h v 9' v 1 +(v 0 -v 1 ) 2024 / 7074 v 9'' v 9 +(v 8 -v 9 ) 5050 / 7074 0ah v 10' v 1 +(v 0 -v 1 ) 1616 / 7074 v 10'' v 9 +(v 8 -v 9 ) 5458 / 7074 0bh v 11' v 1 +(v 0 -v 1 ) 1286 / 7074 v 11'' v 9 +(v 8 -v 9 ) 5788 / 7074 0ch v 12' v 1 +(v 0 -v 1 ) 988 / 7074 v 12'' v 9 +(v 8 -v 9 ) 6086 / 7074 0dh v 13' v 1 +(v 0 -v 1 ) 722 / 7074 v 13'' v 9 +(v 8 -v 9 ) 6352 / 7074 0eh v 14' v 1 +(v 0 -v 1 ) 456 / 7074 v 14'' v 9 +(v 8 -v 9 ) 6618 / 7074 0fh v 15' v 1 +(v 0 -v 1 ) 220 / 7074 v 15'' v 9 +(v 8 -v 9 ) 6854 / 7074 10h v 16' v 1 v 16'' v 8 11h v 17' v 2 +(v 1 -v 2 ) 2058 / 2262 v 17'' v 8 +(v 7 -v 8 ) 204 / 2262 12h v 18' v 2 +(v 1 -v 2 ) 1854 / 2262 v 18'' v 8 +(v 7 -v 8 ) 408 / 2262 13h v 19' v 2 +(v 1 -v 2 ) 1682 / 2262 v 19'' v 8 +(v 7 -v 8 ) 580 / 2262 14h v 20' v 2 +(v 1 -v 2 ) 1526 / 2262 v 20'' v 8 +(v 7 -v 8 ) 736 / 2262 15h v 21' v 2 +(v 1 -v 2 ) 1370 / 2262 v 21'' v 8 +(v 7 -v 8 ) 892 / 2262 16h v 22' v 2 +(v 1 -v 2 ) 1228 / 2262 v 22'' v 8 +(v 7 -v 8 ) 1034 / 2262 17h v 23' v 2 +(v 1 -v 2 ) 1086 / 2262 v 23'' v 8 +(v 7 -v 8 ) 1176 / 2262 18h v 24' v 2 +(v 1 -v 2 ) 944 / 2262 v 24'' v 8 +(v 7 -v 8 ) 1318 / 2262 19h v 25' v 2 +(v 1 -v 2 ) 802 / 2262 v 25'' v 8 +(v 7 -v 8 ) 1460 / 2262 1ah v 26' v 2 +(v 1 -v 2 ) 676 / 2262 v 26'' v 8 +(v 7 -v 8 ) 1586 / 2262 1bh v 27' v 2 +(v 1 -v 2 ) 550 / 2262 v 27'' v 8 +(v 7 -v 8 ) 1712 / 2262 1ch v 28' v 2 +(v 1 -v 2 ) 440 / 2262 v 28'' v 8 +(v 7 -v 8 ) 1822 / 2262 1dh v 29' v 2 +(v 1 -v 2 ) 330 / 2262 v 29'' v 8 +(v 7 -v 8 ) 1932 / 2262 1eh v 30' v 2 +(v 1 -v 2 ) 220 / 2262 v 30'' v 8 +(v 7 -v 8 ) 2042 / 2262 1fh v 31' v 2 +(v 1 -v 2 ) 110 / 2262 v 31'' v 8 +(v 7 -v 8 ) 2152 / 2262 20h v 32' v 2 v 32'' v 7 21h v 33' v 3 +(v 2 -v 3 ) 1570 / 1680 v 33'' v 7 +(v 6 -v 7 ) 110 / 1680 22h v 34' v 3 +(v 2 -v 3 ) 1460 / 1680 v 34'' v 7 +(v 6 -v 7 ) 220 / 1680 23h v 35' v 3 +(v 2 -v 3 ) 1366 / 1680 v 35'' v 7 +(v 6 -v 7 ) 314 / 1680 24h v 36' v 3 +(v 2 -v 3 ) 1272 / 1680 v 36'' v 7 +(v 6 -v 7 ) 408 / 1680 25h v 37' v 3 +(v 2 -v 3 ) 1178 / 1680 v 37'' v 7 +(v 6 -v 7 ) 502 / 1680 26h v 38' v 3 +(v 2 -v 3 ) 1068 / 1680 v 38'' v 7 +(v 6 -v 7 ) 612 / 1680 27h v 39' v 3 +(v 2 -v 3 ) 958 / 1680 v 39'' v 7 +(v 6 -v 7 ) 722 / 1680 28h v 40' v 3 +(v 2 -v 3 ) 864 / 1680 v 40'' v 7 +(v 6 -v 7 ) 816 / 1680 29h v 41' v 3 +(v 2 -v 3 ) 754 / 1680 v 41'' v 7 +(v 6 -v 7 ) 926 / 1680 2ah v 42' v 3 +(v 2 -v 3 ) 660 / 1680 v 42'' v 7 +(v 6 -v 7 ) 1020 / 1680 2bh v 43' v 3 +(v 2 -v 3 ) 550 / 1680 v 43'' v 7 +(v 6 -v 7 ) 1130 / 1680 2ch v 44' v 3 +(v 2 -v 3 ) 456 / 1680 v 44'' v 7 +(v 6 -v 7 ) 1224 / 1680 2dh v 45' v 3 +(v 2 -v 3 ) 346 / 1680 v 45'' v 7 +(v 6 -v 7 ) 1334 / 1680 2eh v 46' v 3 +(v 2 -v 3 ) 220 / 1680 v 46'' v 7 +(v 6 -v 7 ) 1460 / 1680 2fh v 47' v 3 +(v 2 -v 3 ) 110 / 1680 v 47'' v 7 +(v 6 -v 7 ) 1570 / 1680 30h v 48' v 3 v 48'' v 6 31h v 49' v 4 +(v 3 -v 4 ) 4786 / 4896 v 49'' v 6 +(v 5 -v 6 ) 110 / 4896 32h v 50' v 4 +(v 3 -v 4 ) 4660 / 4896 v 50'' v 6 +(v 5 -v 6 ) 236 / 4896 33h v 51' v 4 +(v 3 -v 4 ) 4534 / 4896 v 51'' v 6 +(v 5 -v 6 ) 362 / 4896 34h v 52' v 4 +(v 3 -v 4 ) 4408 / 4896 v 52'' v 6 +(v 5 -v 6 ) 488 / 4896 35h v 53' v 4 +(v 3 -v 4 ) 4266 / 4896 v 53'' v 6 +(v 5 -v 6 ) 630 / 4896 36h v 54' v 4 +(v 3 -v 4 ) 4124 / 4896 v 54'' v 6 +(v 5 -v 6 ) 772 / 4896 37h v 55' v 4 +(v 3 -v 4 ) 3998 / 4896 v 55'' v 6 +(v 5 -v 6 ) 898 / 4896 38h v 56' v 4 +(v 3 -v 4 ) 3810 / 4896 v 56'' v 6 +(v 5 -v 6 ) 1086 / 4896 39h v 57' v 4 +(v 3 -v 4 ) 3622 / 4896 v 57'' v 6 +(v 5 -v 6 ) 1274 / 4896 3ah v 58' v 4 +(v 3 -v 4 ) 3402 / 4896 v 58'' v 6 +(v 5 -v 6 ) 1494 / 4896 3bh v 59' v 4 +(v 3 -v 4 ) 3182 / 4896 v 59'' v 6 +(v 5 -v 6 ) 1714 / 4896 3ch v 60' v 4 +(v 3 -v 4 ) 2946 / 4896 v 60'' v 6 +(v 5 -v 6 ) 1950 / 4896 3dh v 61' v 4 +(v 3 -v 4 ) 2586 / 4896 v 61'' v 6 +(v 5 -v 6 ) 2310 / 4896 3eh v 62' v 4 +(v 3 -v 4 ) 2022 / 4896 v 62'' v 6 +(v 5 -v 6 ) 2874 / 4896 3fh v 63' v 4 v 63'' v 5 out p ut volta g e1 out p ut volta g e2
data sheet s15996ej1v0ds 9 pd16772b 6. relationship between input data and output pin data format : 6 bits x 2 rgbs (6 dots) input width : 36 bits (2-pixel data) (1) r,/l = h (right shift) output s 1 s 2 s 3 s 4 """ s 479 s 480 data d 00 to d 05 d 10 to d 15 d 20 to d 25 d 30 to d 35 """ d 40 to d 45 d 50 to d 55 (2) r,/l = l (left shift) output s 1 s 2 s 3 s 4 """ s 479 s 480 data d 00 to d 05 d 10 to d 15 d 20 to d 25 d 30 to d 35 """ d 40 to d 45 d 50 to d 55 pol s 2n?1 note s 2n note lv 0 to v 4 v 5 to v 9 hv 5 to v 9 v 0 to v 4 note s 2n?1 (odd output), s 2n (even output) 7. relationship between stb, pol and output waveform the output voltage is written to the lcd panel synchronized with the stb falling edge. selected voltage v 0 to v 4 hi-z stb pol s 2n s 2n-1 hi-z hi-z selected voltage v 5 to v 9 selected voltage v 0 to v 4 selected voltage v 0 to v 4 selected voltage v 5 to v 9 selected voltage v 5 to v 9
data sheet s15996ej1v0ds 10 pd16772b 8. relationship between stb, clk and output waveform figure 8?1. output circuit block diagram dac + ? output amp sw1 s n (v x ) v amp(in) figure 8?2. output circuit timing waveform stb s n (v x ) clk v amp(in) hi-z [1] [1'] t stb-clk sw1: off the output voltage is written to the lcd panel synchronized with the stb falling edge. stb = h is loaded with the rising edge of clk [1]. however, when not satisfying the specification of t stb-clk , stb = h is loaded with the rising edge of the next clk [1']. latch operation of display data is completed with the falling edge of the next clk which loaded stb = h. therefore, in order to complete latch operation of display data, it is necessary to input at least 2 clk in stb = h period. besides, after loading stb = h to the timing of [1], it is necessary to continue inputting clk.
data sheet s15996ej1v0ds 11 pd16772b 9. current consumption reduction function the pd16772b has a low power control function (lpc) which can switch the bias current of the output amplifier between two levels and a bias control function (bcont) which can be used to finely control the bias current. ? low power control function (lpc) the bias current of the output amplifier can be switched between two levels using this pin (bcont: open). lpc = h or open: low power mode lpc = l: normal power mode the v dd2 of static current consumption can be reduced to two thirds of that in normal mode. input a stable dc current (v dd1 /v ss1 ) to this pin. ? bias current control function (bcont) it is possible to fine-control the current consumption by using the bias current control function (bcont pin). when using this function, connect this pin to the stabilized ground potential (v ss2 ) via an external resistor (r ext ). when not using this function, leave this pin open. figure 9?1. bias current control function (bcont) pd16772b b cont lpc r ext h/l v ss2 refer to the table below for the percentage of current regulation when using the bias current control function. table 9?1. current consumption regulation percentage compared to normal mode (v dd1 = 3.3 v, v dd2 = 8.7 v) current consumption regulation percentage (%) r ext (k ? ) lpc = l lpc = h/open (open) 100 65 50 120 80 20 140 100 0 240 210 remark the above current consumption regulation percentages are not product-characteristic guaranteed as they re based on the results of simulation. caution because the low-power and bias-current control functions control the bias current in the output amplifier and regulate the over-all current consumption of the driver ic, when this occurs, the characteristics of the output amplifier will simultaneously change. therefore, when using these functions, be sure to sufficiently evaluate the picture quality.
data sheet s15996ej1v0ds 12 pd16772b 10. electrical specifications absolute maximum ratings (t a = 25 c, v ss1 = v ss2 = 0 v) parameter symbol rating unit logic part supply voltage v dd1 ?0.5 to +4.0 v driver part supply voltage v dd2 ?0.5 to +10.0 v logic part input voltage v i1 ?0.5 to v dd1 + 0.5 v driver part input voltage v i2 ?0.5 to v dd2 + 0.5 v logic part output voltage v o1 ?0.5 to v dd1 + 0.5 v driver part output voltage v o2 ?0.5 to v dd2 + 0.5 v operating ambient temperature t a ?10 to +75 c storage temperature t stg ?55 to +125 c caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. recommended operating range (t a = ?10 to +75 c, v ss1 = v ss2 = 0 v) parameter symbol condition min. typ. max. unit logic part supply voltage v dd1 2.3 3.6 v driver part supply voltage v dd2 8.0 8.5 9.0 v high-level input voltage v ih 0.7 v dd1 v dd1 v low-level input voltage v il 00.3 v dd1 v v 0 to v 4 0.5 v dd2 v dd2 ? 0.1 v -corrected voltage v 5 to v 9 0.1 0.5 v dd2 v driver part output voltage v o 0.1 v dd2 ? 0.1 v clock frequency f clk v dd1 = 2.3 v 45 mhz
data sheet s15996ej1v0ds 13 pd16772b electrical characteristics (t a = ?10 to +75 c, v dd1 = 2.3 to 3.6 v, v dd2 = 8.5 v 0.5 v, v ss1 = v ss2 = 0 v, unless otherwise specified, the input level is defined to be lpc = l, bcont = open) parameter symbol condition min. typ. max. unit except lpc 1.0 a input leak current i il lpc t.b.d. t.b.d. a high-level output voltage v oh sthr (sthl), i oh = 0 ma v dd1 ? 0.1 v low-level output voltage v ol sthr (sthl), i ol = 0 ma 0.1 v -corrected resistance r v 0 to v 4 = v 5 to v 9 = 4.0 v t.b.d. t.b.d. t.b.d. k ? i voh v x = 7.0 v, v out = 6.5 v note ?30 a driver output current i vol v x = 1.0 v, v out = 1.5 v note 30 a output voltage deviation ? v o 7 20 mv output swing difference deviation ? v p?p t a = 25 c, v dd1 = 3.3 v, v dd2 = 8.5 v, v out = 2.0 v, 4.25 v, 6.5 v 2 15 mv logic part dynamic current consumption i dd1 v dd1 1.0 7.5 ma driver part dynamic current consumption i dd2 v dd2 , with no load 3.5 7.5 ma note v x refers to the output voltage of analog output pins s 1 to s 480 . v out refers to the voltage applied to analog output pins s 1 to s 480 . remark t.b.d. (to be determined.) cautions 1. f stb = 50 khz, f clk = 40 mhz. 2. the typ. values refer to an all black or all white input pattern. the max. value refers to the measured values in the dot checkerboard input pattern. 3. refers to the current consumption per driver when cascades are connected under the assumption of uxga single-sided mounting (10 units). switching characteristics (t a = ?10 to +75 c, v dd1 = 2.3 to 3.6 v, v dd2 = 8.5 v 0.5 v, v ss1 = v ss2 = 0 v, unless otherwise specified, the input level is defined to be lpc = l, bcont = open) parameter symbol condition min. typ. max. unit start pulse delay time t plh1 c l = 10 pf 10 20 ns t phl1 10 20 ns driver output delay time t plh2 2.5 5 s t plh3 58 s t phl2 2.5 5 s t phl3 c l = 75 pf, r l = 5 k ? 58 s input capacitance c i1 sthr (sthl) excluded, t a = 25c 5 10 pf c i2 sthr (sthl), t a = 25c 8 10 pf gnd c l1 c l2 c l3 c l4 c l5 r l1 r l2 r l3 r l4 r l5 r ln = 1 k ? c ln = 15 pf measurement point output
data sheet s15996ej1v0ds 14 pd16772b timing requirements (t a = ?10 to +75 c, v dd1 = 2.3 to 3.6 v, v ss1 = 0 v, t r = t f = 5.0 ns) parameter symbol condition min. typ. max. unit clock pulse width pw clk 22 ns clock pulse high period pw clk(h) 4ns 2.3 v v dd1 < 3.0 v 7ns clock pulse low period pw clk(l) 3.0 v v dd1 3.6 v 4ns data setup time t setup1 3ns data hold time t hold1 0ns start pulse setup time t setup2 3ns start pulse hold time t hold2 0ns pol21, pol22 setup time t setup3 3ns 2.3 v v dd1 < 3.0 v 1ns pol21, pol22 hold time t hold3 3.0 v v dd1 3.6 v 0ns stb pulse width pw stb 2clk last data timing t ldt 2clk clk-stb time t clk-stb clk stb 6ns stb-clk time t stb-clk stb clk 2.3 v v dd1 < 3.0 v 14 ns stb clk 3.0 v v dd1 3.6 v 6ns time between stb and start pulse t stb-sth stb sthr(sthl) 2clk pol-stb time t pol-stb pol or stb ?5 ns stb-pol time t stb-pol stb pol or 6ns remark unless otherwise specified, the input level is defined to be v ih = 0.7 v dd1 , v il = 0.3 v dd1 .
data sheet s15996ej1v0ds 15 pd16772b switching characteristic waveform (r,/l = h) unless otherwise specified, the input level is defined to be v ih = 0.7 v dd1 , v il = 0.3 v dd1 . pw clk(l) clk pol (v x ) s n stb d n0 to d n5 sthr sthl pw clk(h) t r t setup2 invalid d 1 to d 6 t hold2 12 12 3646566 513 514 t f v dd1 v ss1 v dd1 v ss1 v dd1 v ss1 v dd1 v ss1 v dd1 v ss1 v dd1 v ss1 pw clk t clk-stb t stb-clk t stb-sth t setup1 90% 10% t hold1 t plh1 t pol-stb t stb-pol t plh3 t plh2 t phl2 t phl3 hi-z target voltage 0.1 v dd2 6-bit accuracy t ldt pw stb d 7 to d 12 d 1 to d 6 d 7 to d 12 d 373 to d 378 d 379 to d 384 d 385 to d 390 d 3067 to d 3072 invalid invalid v dd1 v ss1 t setup3 t hold3 pol21, pol22 (1st dr.) (1st dr.) invalid t phl1
data sheet s15996ej1v0ds 16 pd16772b 11. recommended mounting conditions the following conditions must be met for mounting conditions of the pd16772b. for more details, refer to the semiconductor device mounting technology manual (c10535e). please consult with our sales offices in case other mounting process is used, or in case the mounting is done under different conditions. pd16772bn- xxx: tcp (tab pack age) mounting condition mounting method condition thermocompression soldering heating tool 300 to 350 c, heating for 2 to 3 seconds : pressure 100 g (per solder) acf (adhesive conductive film) temporary bonding 70 to 100 c : pressure 3 to 8 kg/cm 2 : time 3 to 5 sec. real bonding 165 to 180 c: pressure 25 to 45 kg/cm 2 : time 30 to 40 sec. (when using the anisotropy conductive film sumizac1003 of sumitomo bakelite, ltd). caution to find out the detailed conditions for mounting the acf part, please contact the acf manufacturing company. be sure to avoid using two or more mounting methods at a time.
data sheet s15996ej1v0ds 17 pd16772b [memo]
data sheet s15996ej1v0ds 18 pd16772b [memo]
data sheet s15996ej1v0ds 19 pd16772b notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function.
pd16772b reference documents nec semiconductor device reliability/quality control system(c10983e) quality grades on nec semiconductor devices(c11531e) m8e 00. 4 the information in this document is current as of july 2002. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec's data sheets or data books, etc., for the most up-to-date specifications of nec semiconductor products. not all products and/or types are available in every country. please check with an nec sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without prior written consent of nec. nec assumes no responsibility for any errors that may appear in this document. nec does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec semiconductor products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. nec assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec endeavours to enhance the quality, reliability and safety of nec semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. nec semiconductor products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. the recommended applications of a semiconductor product depend on its quality grade, as indicated below. customers must check the quality grade of each semiconductor product before using it in a particular application. "standard": computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "special": transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "specific": aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. the quality grade of nec semiconductor products is "standard" unless otherwise expressly specified in nec's data sheets or data books, etc. if customers wish to use nec semiconductor products in applications not intended by nec, they must contact an nec sales representative in advance to determine nec's willingness to support a given application. (note) (1) "nec" as used in this statement means nec corporation and also includes its majority-owned subsidiaries. (2) "nec semiconductor products" means any semiconductor product developed or manufactured by or for nec (as defined above). ? ? ? ? ? ?

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